1. Field of the Invention
The present invention relates to a semiconductor wafer, more specifically to a silicon-on-insulator type silicon semiconductor wafer or SOI wafer having an insulating layer inserted between an upper and a lower silicon semiconductor portions thereof, and a process for producing the same.
2. Description of the Related Art
An SOI wafer has a structure in which an insulating layer is inserted between an upper wafer portion of single crystalline silicon for forming electronic elements thereon (hereinafter referred to as "element wafer portion") and a lower wafer portion of single crystalline silicon acting as a support for the entire wafer (hereinafter referred to as "support wafer portion").
A conventional SOI wafer has a structure as shown in FIG. 1A, in which an insulating layer 13 is simply inserted between upper and lower silicon semiconductor portions 11 and 12 of a wafer 10' to form a "sandwich" structure, the insulating layer 13 being exposed at the periphery of the wafer 10'.
The insulating layer 13 is preferably formed of silicon oxide for ensuring good interface characteristics between the insulating layer 13 and the overlying element wafer portion 11 formed of silicon.
Nevertheless, the production of semiconductor devices includes etching of various silicon oxide films, during which the silicon oxide layer 13 of an SOI structure is also etched in the circumferential portion 14 of the wafer 10' to cause the silicon oxide layer 13 to regress from the circumference 14 of the wafer 10', and thereby, the element wafer portion 11 relatively protrudes to form eaves 17, as shown in FIG. 1B. The element wafer portion 11 usually is as thin as about 1 to 5 microns and has a mechanical strength so poor that the protruded eaves 17 are easily broken or worn off during various treatments and handling of the wafer 10'. The broken or worn off silicon particles stick to the wafer surface as dust, which causes a pattern defect or a defect of deposited layers and leads to poor product yield.